read :

following are the details: < s >: start signal scl sda high high high low the start signal is high to low transition on the sd a line when scl is high. < write sa >: write slave address: 70h or 72h < read sa >: read slave address: 71h or 73h < register index >: value of the AL300 register index. < a >: acknowledge stage the acknowledge - related clock pulse is generated by the host (master). the host releases the sda line (high) for the AL300 (slave) to scl sda sda scl sda scl scl sda scl data bit [1] or na data bit [0] or a start bit [s] stop bit [p] not significant al250-15 i2c drawing
AL300 november 28 , 2001 29 pull down the sda line during the acknowledge clock pulse. < na >: not acknowledged stage the acknowledge - related clock pulse is generated by the host (master). the host releases the sda line (high) during the acknowledge clock pulse, but the AL300 does not pull it down during this stage. < data >: data byte write to or read from the register index. in read operation, the host must release the sda line (high) before the first clock pu lse is transmitted to the AL300. < p >: stop signal scl sda high low high high the stop signal is low to high transition on the sda line when scl is high. suppose data f0h is to be written to register 0fh using write slave address 70h, the timing is as fo llows: suppose data is to be read from register 55h using read slave address 71h, the timing is as follows: start slave addr = 70h ack ack ack stop index = 0fh data = f0h sda scl AL300-13 i2c write timing
AL300 november 28 , 2001 30 more information on the AL300 functionality can be found in the register definition section. start slave addr = 70h ack ack ack index = 55h read slave addr = 71h sda scl AL300-14 i2c read timing nack stop data read cycle stop start
AL300 november 28 , 2001 31 7.0 electrical characteristics 7.1 recommended operating conditions parameter min max unit vdd supply voltage +3.0 +4.0 v tamb ambient operating temperature 0 +70 c 7.2 characteristics parameter test conditions min max unit i dd supply current 80 300 ma p power consumption 240 1200 mw v ih hi - level input voltage 0.7vdd 5.5 v v il lo - level input voltage - 0.5 +0.8 v v oh hi - level output voltage 2.4 vdd v v ol lo - level output voltage - 0.5 v i o output current, data - 0.5v AL300 november 28 , 2001 32 7.3 timing diagram AL300 input timing tvclk/ gclk r/yin[7:0] g/uvin[7:0] bin[7:0] t ck t ckh t ckl t ih t is AL300 single pixel output timing sclk ra[7:0] ga[7:0] ba[7:0] t ck2 t oh t ck2h t ck2l t pd t f t r AL300 dual pixel output timing pclkb t pd t oh sclk pclka ra[7:0] ga[7:0] ba[7:0]
AL300 november 28 , 2001 33 8. 0 AL300 register definition following is the summary of the AL300 control registers: register r/w address function configuration companyid r 00h company id (46h) revision r 01h revision number boardconfig r/w 02h board configuration general r/w 03h general control family r 04h chip family number polarity r/w 05h polarity control dither r/w 06h dither control adjustment r/w 07h adjustment control output clock pll and zoom ratio plldiv r/w 10h, 11h pll divider number pllrefdiv r/w 12h, 13h displ ay pll reference input divider number hratio r/w 14h, 15h horizontal scale ratio vratio r/w 16h, 17h vertical scale ratio hinitphase r/w 18h horizontal zoom scaler initial phase vinitphaseodd r/w 19h vertical zoom scalar initial phase in odd field of i nterlaced input vinitphase r/w 1ah vertical zoom scalar initial phase gout r/w 1bh panel power control input timing caphstart r/w 20h, 21h horizontal capture start position caphend r/w 22h horizontal capture size resettest r/w 23h testing capvstart r/w 24h, 25h vertical capture start position capvend r/w 26h, 27h vertical capture end position framevstart r/w 28h, 29h display vertical counter start position relative to input vertical counter
AL300 november 28 , 2001 34 output timing dsphtotal r/w 30h, 31h display horizontal total dsphsend r/w 32h output display horizontal sync end position dsphdestart r/w 33h output horizontal display start dsphdeend r/w 34h output horizontal display end dspvsend r/w 35h output display vertical sync end position blinkctrl r/w 36h osd bli nking control dspvdestart r/w 37h, 38h output vertical display start position dspvdeend r/w 39h, 3ah output vertical display end position framedelay r/w 3bh output hsync delay adjustment relative to input hsync framedelayodd r/w 3ch output hsync delay adjustment relative to input hsync in odd field interrupt and internal timing ireqsource r/w 40h interrupt source refhtotal r/w 41h horizontal total of internal reference timing refvtotal r/w 42h vertical total of internal reference timing outputcontr ol r/w 43h output control look - up table rlutport r/w 48h red lut write data port glutport r/w 49h green lut write data port blutport r/w 4ah blue lut write data port lutwaddr r/w 4bh address of lut wrote port osd ram osdramwaddr r/w 4ch, 4dh osd ram write address osdramwport r/w 4eh osd ram write port blanking/border control hblankstart r/w 50h, 51h horizontal blank start hblankend r/w 52h, 53h horizontal blank end vblankstart r/w 54h, 55h vertical blank start vblankend r/w 56h, 57h vertical bl ank end input timing measurement inputstatus r 60h input status linerate r 61h, 62h input line rate, which is counted by clock from xin pin
AL300 november 28 , 2001 35 invtotal r 63h, 64h total vertical line count of input video ireqstatus r 65h interrupt status inhtotal r 66h, 67h input horizontal pixel total automatic positioning hlinenumber r/w 70h horizontal line number for horizontal active start and end detection datathreshold r/w 71h data threshold value used to determine non - blanking pixel hdestart r 72h, 73h detecte d horizontal active start pixel position hdeend r 74h, 75h detected horizontal active end pixel position vcolumn r/w 79h vertical column for vertical active start and end detection vdestart r 7ah, 7bh detected vertical active start line vdeend r 7ch, 7 dh detected vertical active end line osd control osdmode r/w 80h osd(on screen display) modes foreop r/w 81h logic operation fadealpha r/w 82h fading alpha value osd 1 osdcontrol1 r/w 84h osd1 control romstartaddr1 r/w 85h osd1 rom start address fo ntaddrunit1 r/w 86h osd1 font address unit osdhstart1 r/w 90h on screen display horizontal start position osdvstart1 r/w 91h on screen display vertical start position ramaddrst1 r/w 92h osd1 ram start address ramstride1 r/w 93h, 8bh osd1 ram line strid e bmaphsize1 r/w 94h, 95h osd1 horizontal bitmap size bmaphtotal1 r/w 96h, 97h osd1 bitmap horizontal total bmapvsize1 r/w 98h, 99h osd1 bitmap vertical size bmapvtotal1 r/w 9ah, 9bh osd1 bitmap vertical total iconhtotal1 r/w 9ch osd1 horizontal icon total iconvtotal1 r/w 9dh osd1 vertical icon total fontlinesize1 r/w aeh osd1 font line size osd 2 osdcontrol2 r/w 88h osd2 control romstartaddr2 r/w 89h osd2 rom start address
AL300 november 28 , 2001 36 fontaddrunit2 r/w 8ah osd2 font address unit osdhstart2 r/w a0h on scree n display horizontal start position osdvstart2 r/w a1h on screen display vertical start position ramaddrst2 r/w a2h osd2 ram start address ramstride2 r/w a3h, 8ch osd2 ram line stride bmaphsize2 r/w a4h, a5h osd2 horizontal bitmap size bmaphtotal2 r/w a6h, a7h osd2 bitmap horizontal total bmapvsize2 r/w a8h, a9h osd2 bitmap vertical size bmapvtotal2 r/w aah,abh osd2 bitmap vertical total iconhtotal2 r/w ach osd2 horizontal icon total iconvtotal2 r/w adh osd2 vertical icon total fontlinesize2 r/w a fh osd2 font line size osd color registers color0red r/w b0h color 0 red component color0green r/w b1h color 0 green component color0blue r/w b2h color 0 blue component color1red r/w b3h color 1 red component color1green r/w b4h color 1 green compone nt color1blue r/w b5h color 1 blue component color2red r/w b6h color 2 red component color2green r/w b7h color 2 green component color2blue r/w b8h color 2 blue component color3red r/w b9h color 3 red component color3green r/w bah color 3 green compo nent color3blue r/w bbh color 3 blue component
AL300 november 28 , 2001 37 8.1 register description configuration: 00h: company id (r) [companyid] companyid <7:0> company id (46h) 01h: revision (r) [revision] revision <7:0> revision number 02h: board configuration (r only; r/w for bit 0) [boardconfig] if softcinfig (0x03<4>) = 0, this register setting represent board configuration. if softcinfig (0x03<4>) = 1, bit 0 (only) is programmable by software. the other bits still represent board configuration. videoin <0> 0 acce pt graphic input 1 accept video input i 2 c <6> 0 serial i 2 c input 1 reserved i 2 c addr <7> 0 i 2 c write address is 70h, read address is 71h. 1 i 2 c write address is 72h, read address is 73h. 03h: general (r/w) [general] pwrdown <0> 0 normal operat ion 1 power down mode softtiming <1> should always be 1 to enable s/w timing configuration. disablepll* <2> should always be 0 to enable internal/external pll. plldivhs <3> 0 use input hsync as the display clock pll input reference to generate output pixel clock. use registers #10h and 11h to define the pll divider. 1 use divided input hsync as display clock pll input reference. it needs to be enabled when required output pll divider is higher than 2047, but can be used any time when output pix el rate is higher than input pixel rate. the divider ratio is defined by registers #10h ~ #13h. refer to registers #10h ~ #13h for additional reference. softconfig <4> 0 input video type is defined by external pin videoin. 1 input video type is de fined by bit 0 of register 02h. refer to register 02h for additional reference. bypass <5> video pass through without scaling. 0 enable scaling defined in registers 14h, 15h, 16h and 17h 1 bypass when in bypass mode, only output timing registers 30h, 31h, 37h, 38h, 39h and 3ah affect the timing control. the pll and input timing registers are ignored. ddr12* <6> reserved. should be always 0. reftiming <7> 0 normal operation 1 free running
AL300 november 28 , 2001 38 in free running mode, external input hsync and vsyn c are disabled. nominal input timing is defined by registers 41h and 42h instead. this is useful when external video source is disconnected or unstable. the reference clock is given by xin pin. refer to registers 36h, 41h and 42h for additional refe rence. 04h: chip family (r) [family] family <7:0> 00110000, AL300 series 05h: polarity (r/w) [polarity] invpllref <0> 0 display clock pll reference signal is of negative polarity 1 display clock pll reference signal is of positive polarity invpllf b <1> 0 display clock pll feedback signal is of negative polarity 1 display clock pll feedback signal is of positive polarity hspol <2> 0 output hsync is of positive polarity 1 output hsync is of negative polarity blnkpol <3> 0 output display enabl e pdspen is of positive polarity 1 output display enable pdspen is of negative polarity vspol <4> 0 output vsync is positive polarity 1 output vsync is negative polarity abdelay <5> delay a data so that a and b data outputs are of the same timing. usually written as 1 for dual pixel panels. nc for single pixel panels. please also program registers #07h and #43h accordingly for dual pixel panels. csyncout <6> 0 normal hsync output 1 send composite sync output from phs pin invoddfiled <7> fo r ccir601 or square pixel video input, this bit should be written as 1 for correct interlaced odd/even field detection. in case of error, rewrite this bit as 0. 06h: dither control (r/w) [dither] sharpness <1:0> sharpness control 00 turn off sharpness control 01 sharpness level 1 10 sharpness level 2 (sharper than level 1) 11 sharpness level 3 (sharpest) reserved <2> reserved <3> should be always 1 for optimized output. dithmode <5:4> dither mode select 00 rgb 888 01 rgb 666 10 rgb 44 4 11 rgb 444 without dithering. it is recommended not to use dithering for graphics input for best sharpness. softtvref <6> 0 yuv video horizontal capture start is defined by the hardware tvref pin
AL300 november 28 , 2001 39 1 yuv video horizontal capture start is defined by re gister #20h and #21h. note that when #20h values changes between odd and even, the output u/v may flip. #20h should stay either odd or even at all times to ensure correct u/v. when softtvref is 0, register#20h<0> will be used as u/v flip the count erpart for controlling graphic reference is defined by softgraref (register #80h<6>) interpolation <7> 0 turn on interpolation 1 turn off interpolation (duplicate pixels only) 07h: adjustment (r/w) [adjustment] reserved <7> hdedelay <6:4> pdspen d elay relative to output data phase reserved <3:0> optimized value is 00h for single pixel mode, 20h for dual pixel mode please also program registers #05h<5>, #43h<7>, and #43h<4> accordingly for dual pixel mode. output clock pll and zoom ratio: the output pixel clock is generated from the input hsync (or with input pixel clock) relative to the ratio between the output and input display resolution. the pll divider (plldiv, defined by registers #10h and 11h) has a maximum value of 2047 programmed by an 11 - bit word. plldiv is defined by the following equation: for the best scaling quality, pllrefdiv (defined by registers #12h and #13h) is used as a pll reference divider. in this case, pllrefdiv (m) should be equal to the total number of pix els per input line (hi). if n is greater than 2047, both n and m need to be adjusted by dividing the scaling ratio by a simple integer as in the following example: example: (n greater than 2047) plldiv(n) = vo vi where, ho is the total number of pixels per output line vo is the output active lines per frame vi is the input active lines per frame ho
AL300 november 28 , 2001 40 vo = 768 vi = 240 ho = 1200 therefore, using the equation for plldiv, n = 3840 which is much greater than 2047. the scaling ratio is: since n is greater than 2047, the scaling ratio can be divided by 2 for the best scaling quality. dividing this ratio by 2, the scaling ratio becomes: these scaled values are ideal for n and m. note: ideally, for the pll, n should be an even integer. 10h: pll divider low (r/w) [plldiv] plldivl <7:0> bits <7:0> of pll divider number 11h: pll divider high (r/w) [plldiv] feb2_d2 <7> feedback divider 2 control 0: bypass feedback divider 2 1: enable feedback divider 2. output clock frequency is doubled when the feedback divider is turned on. feb1_d2 <6> feedback divider 1 control 0: bypass feedback divider 1 1: enable feedback divider 1. output clock frequency i s doubled when the feedback divider is turned on. out_d2 <5> output 1 - bit divider control 0: bypass output divider 2 1: enable output divider 2. output clock frequency is divided by 2 when the output divider is turned on. pre_d2 <4> input 1 - bit div ider control 0: bypass input divider 2 1200 1024 768 858 240 720 input display output display n m 3840 858 n m 1920 429
AL300 november 28 , 2001 41 1: enable input divider 2. output clock frequency is divided by 2 when the input divider is turned on. plldivh (10:8) <2:0> bits 8~10 of the pll divider the value of plldiv is determined by subtracting from th e actual target divider by 2 when internal pll is used. for example, if the desired divider value is 840, then the value set to the related registers should be 838 = 346h. therefore, plldivh[2:0] should be set to 3h (?011?) and plldivl[7:0] should be set to 46h (?01000110?). however, when an external genlock pll such as ics9173 is used, programming registers 10h and 11h is still needed. in such applications, the plldiv should be the actual target divider instead of being subtracted by 2 as in the above c ase. please review the AL300programming algorithm for more details. 12h: pll reference divider low (r/w) [pllrefdiv] pllrefdivl <7:0> bits <7:0> of display pll reference input divider number (unit: 1 pixel) 13h: pll reference divider high (r/w) [pllrefd iv] pllrefdivh <2:0> bits <10:8> of display pll reference input divider number registers 14h~17h are used to define the independent horizontal and vertical scaling ratio. 14h: horizontal zoom ratio low (r/w) [hratio] hratiol <7:0> bits <7:0> of hori zontal scale ratio value valid only when register 03h<5> = 0. 15h: horizontal zoom ratio high (r/w) [hratio] hratioh <2:0> bits <10:8> of horizontal scale ratio value valid only when register 03h<5> = 0. horizontal zoom ratio = (hdst x 256) / hsrc hsrc = horizontal source capture size (register 22h) hdst = horizontal destination active width (registers 33h and 34h) 16h: vertical zoom ratio low (r/w) [vratio] vratiol <7:0> bits <7:0> of vertical scale ratio value valid only when register 03h<5> = 0. 17h: vertical zoom ratio high (r/w) [vratio] vratioh <6:0> bits <14:8> of vertical scale ratio value valid only when register 03h<5> = 0. vertical zoom ratio = (vdst x 4096) / vsrc
AL300 november 28 , 2001 42 vsrc = (output vertical active line count x output horizontal line total) / n, or (voa x hot) / n. this value should be very close to vertical source active lines (register 24h, 25h, 26h and 27h), but please keep the decimal. vdst = vertical destination active lines (registers 37h, 38h, 39h and 3ah) note: when v ertical zoom ratio is to be changed, input capture timing, pll divider and m/n values should also be modified. please refer to the AL300 programming algorithm for detailed description. 18h: horizontal zoom initial phase (r/w) [hinitphase] hinitph <7:0> horizontal zoom scaler initial phase the purpose of phase adjustment is to optimize the scaling quality when the scaling ratio is a simple fraction such as 2/1 or 3/2. the initial interpolation phase can be 0 up to close to 1 pixel, hinitph = (1 ? hia/2 /hoa) x 32. please refer to the AL300 programming algorithm for detailed description. the vertical counterpart is defined by register #1ah 19h: vertical zoom initial phase at odd field (r/w) [vinitphaseodd] vinitphodd <7:0> vertical zoom scalar initial phase for the odd field of interlaced input. enter the same value as register 1ah for non - interlaced input. refer to the AL300 programming algorithm for more details. 1ah: vertical zoom initial phase (r/w) [vinitphase] vinitph <7:0> vertical zoom scalar initial phase. this is the initial phase for graphics input or even field of interlaced input. the recommended value is 20h. the horizontal zoom initial phase is defined by register #18h 1bh: panel power control (r/w) [gout] controlen <0> ena ble panel interface control signals gout3 <1> general purpose register for gout3 pin. gout1 <2> general purpose register for gout1 pin. gout2 <3> general purpose register for gout2 pin. the gout bits are reserved in case additional control pins are r equired for specific panels. yuv444in <4> 0 yuv422 input 1 yuv444 input (set <5>=0) ccir601 <5> 0 ccir601 input timing format 1 reserved yuvout <6> 0 rgb output 1 yuv output yuv444out <7> 0 yuv422 output 1 yuv444 output bits<7:4> is vali d only if register #02h<0>, videoin is 1 input timing:
AL300 november 28 , 2001 43 please refer to section 6.5 input video timing for additional reference. the input timing diagram (AL300 - 07) shows it pictorially. 20h: horizontal capture start low (r/w) [caphstart] caphstartl <7: 0> bits<7:0> of horizontal capture start position (unit: 1 pixel) 21h: horizontal capture start high (r/w) [caphstart] caphstarth <2:0> bits <10:8> of horizontal capture start position 22h: horizontal capture size (r/w) [caphsize] caphsize <7:0> horizo ntal capture size (unit: 8 pixels) 23h: testing (r/w) [resettest] reserved <7:0> reserved 24h: vertical capture start low (r/w) [capvstart] capvstarth <7:0> bits <7:0> of vertical capture start position (unit: 1 line) 25h: vertical capture start high (r/w) [capvstart] capvstartl <2:0> bits <10:8> of vertical capture start position 26h: vertical capture end low (r/w) [capvend] capvendl <7:0> bits <7:0> of vertical capture end position (unit: 1 line) 27h: vertical capture end high (r/w) [capvend] capvendh <2:0> bits <10:8> of vertical capture end position registers #28h and #29h are used to control the delay of vertical lines between the output and the input. the counterpart for horizontal delay is controlled by the registers #3bh and #3ch. 2 8h: vertical display frame start position low (r/w) [framevstart] framevstartl <7:0> bits <7:0> of display vertical counter start position relative to input vertical counter. (unit: 1 line) 29h: vertical display frame start position high (r/w) [framevsta rt] framevstarth <2:0> bits <10:8> of display vertical counter start position relative to input vertical counter. output timing: please refer to section 6.6 output video timing for additional reference. the output timing diagram (AL300 - 08) shows it pic torially. 30h: horizontal total low (r/w) [dsphtotal] dsphtotall <7:0> bits <7:0> of display horizontal total. (unit: 1 pixel)
AL300 november 28 , 2001 44 31h: horizontal total high (r/w) [dsphtotal] dsphtotalh <2:0> bits <10:8> of display horizontal total. 32h: horizontal sync end (r/w) [dsphsend] dsphsend <7:0> output display horizontal sync end position (unit: 8 pixels) 33h: horizontal display start (r/w) [dsphdestart] dsphdestart <7:0> output horizontal display start (unit: 8 pixels) 34h: horizontal display end (r/w) [dsp hdeend] dsphdeend <7:0> output horizontal display end (unit: 8 pixels) 35h: vertical sync end (r/w) [dspvsend] dspvsend <7:0> output display vertical sync end position (unit: 8 line) 36h: blink control (r/w) [blinkctrl] blinktime <1:0> osd blinking ti me constant 00 32 frames of internal reference timing per blink 01 64 frames of internal reference timing per blink 10 128 frames of internal reference timing per blink 11 256 frames of internal reference timing per blink (refer to registers 41h, 42h, 84h<1> and 88h<1> for additional reference) blinktype <2> 0 blinking is defined in blinktime 1 no blinking, just reverse the index color 37h: vertical display start low (r/w) [dspvdestart] dspvdestartl <7:0> bits <7:0> of vertical display start position. (unit: 1 line) 38h: vertical display start high (r/w) [dspvdestart] dspvdestarth <2:0> bits <10:8> of vertical display start position. 39h: vertical display end low (r/w) [dspvdeend] dspvdeendl <7:0> bits <7:0> of vertical display end position. (unit: 1 line) 3a: vertical display end high (r/w) [dspvdeend] dspvdeendh <2:0> bits <10:8> of vertical display end position. registers #3bh and #3ch are used to control the delay of horizontal pixels between the output and the input. the counterpart for vertical delay is controlled by the registers #28h and #29h. 3b: frame head delay adjustment (r/w) [framedelay] framedly <7:0> output hsync delay adjustment relative to input hsync (unit: 16 pixels) refer to the AL300 programming algorit hm for more details. 3c: frame head delay adjustment for odd field (r/w) [framedelayodd]
AL300 november 28 , 2001 45 framedlyodd <7:0> output hsync delay adjustment relative to input hsync in odd field. (unit: 16 pixels) for non - interlaced video, framedlyodd has the same value as framedly. for interlaced video, framedlyodd is half line more than framedly. refer to the AL300 programming algorithm for more details. interrupt and internal timing: 40h: interrupt source (r/w) [ireqsource] linerateireq <0> if 1, enable interrup t if line rate changes vsyncireq <1> if 1, enable interrupt if vsync comes oddfieldireq <2> if 1, enable interrupt when odd field of input video comes to check what causes the interruption when more than one interrupt source is enabled, read register # 65h for the status and then clear it for the next interruption. 41h: reference h total (r/w) [refhtotal] refhtotal <7:0> horizontal total of internal reference timing (unit: 8 pixels). enabled when register 03h <7>=1 registers #41h and #42h are used to define free running mode when input is disconnected or is undefined. this is especially useful for showing error messages with osd. refer to register #42h for examples. 42h: reference v total (r/w) [refvtotal] refvtotal <7:0> vertical total of inte rnal reference timing (unit: 8 lines) enabled when register 03h <7>=1 register 41h and 42h are used to define free running mode when input is disconnected or is undefined. this is especially useful for showing error message with osd. for instance, a reference clock of 14.31818 mhz is used to generate hsync and vsync with vertical frame refresh rate of 60hz, the resulted h - total and v - total would be as follows: panel h - total (reg.#41h x 8) v - total (reg.#42h x 8) 640x480: 456 520 800x600: 376 632 1024x768: 296 800 1280x1024 216 1072 to correct the h - total if necessary, program the input pll circuitry to generate correct input pixel clock rate. 43h: output control (r/w) [outputcontrol] reserved <2:0> should be written as 000. noblank <3> no b lanking, all data pass through; for testing only. dualout <4> output odd/even pixels for dual pixel panels luten <5> enable lut
AL300 november 28 , 2001 46 colorout <6> replace the input video with color 3 (refer to registers #b9h, #bah, and #bbh for additional reference) invoutc lk <7> invert the phase of sclk, pclka, and pclkb. this bit is usually 1 for dual pixel panels. please also program registers #05h and #07h accordingly for dual pixel panels. 65h: interrupt status (r only) [ireqstatus] please refer to the register 65h d escription in the input timing measurement section, after register 64h. look - up table: 48h: red lut write data port (r/w) [rlutport] rlutport <7:0> red lut write data port 49h: green lut write data port (r/w) [glutport] glutport <7:0> green lut write data port 4ah: blue lut write data port (r/w) [blutport] blutport <7:0> blue lut write data port 4bh: lut write port address (r/w) [ lutwaddr] lutwraddr <7:0> address of lut wrote port osd ram: 4ch: osd ram address low byte (r/w) [osdramwaddr] osd ramaddrl <7:0> bits <7:0> of osd ram write address 4dh: osd ram address high byte (r/w) [osdramwaddr ] osdramaddrh<1:0> bits <9:8> of osd ram write address 4eh: osd ram write data port (r/w) [osdramwport] osdramport <7:0> osd ram write port writing da ta to this register #4eh automatically increases the osd ram address defined in registers #4ch and #4dh. blanking/border control: the blanking control is used as output data cropping 50h: horizontal blank start low (r/w) [hblankstart] hblankstartl < 7:0> bits <7:0> of horizontal blank start position + 12. (unit: 1 pixel)
AL300 november 28 , 2001 47 51h: horizontal blank start high (r/w) [hblankstart] hblankstarth <2:0> bits <10:8> of horizontal blank start position + 12. (unit: 1 pixel) 52h: horizontal blank end low (r /w) [hblankend] hblankendl <7:0> bits <7:0> of horizontal blank end position + 12. (unit: 1 pixel) 53h: horizontal blank end high (r/w) [hblankend] hblankendh <2:0> bits <10:8> of horizontal blank end position + 12. (unit: 1 pixel) 54h: vertical blan k start low (r/w) [vblankstart] vblankstartl <7:0> bits <7:0> of vertical blank start position. (unit: 1 line) 55h: vertical blank start high (r/w) [vblankstart] vblankstarth <2:0> bits <10:8> of vertical blank start position. (unit: 1 line) 56h: ver tical blank end low (r/w) [vblankend] vblankendl <7:0> bits <7:0> of vertical blank end position. (unit: 1 line) 57h: vertical blank end high (r/w) [vblankend] vblankendh <2:0> bits <10:8> of vertical blank end position. (unit: 1 line) input timing measurement: 60h: input status (r only) [inputstatus] inhspol <0> input hsync polarity. 0 active low/ negative polarity 1 active high/ positive polarity invspol <1> input vsync polarity. 0 active low/ negative polarity 1 active high/ posit ive polarity oddfield <2> 1, if input is in odd field reserved <3> invde <4> 1, if input video is in active region outvde <5> 1, if output video is in active region refvs <6> 1, if refence timing is in vsync cycle (in free running mode) invsync <7> 1 , if input timing is in vysnc cycle 61h: input line rate low (r only) [linerate] lineratel <7:0> bits <7:0> of input line rate, which is in terms of how many reference lock cycles per horizontal line. refresh rate = (reference clock frequency) / (liner ate x invtotal) reference clock is the clock from xin pin. linerate is the input line rate defined in registers #61h and #62h invtotal is the input vertical total line defined in registers #63h and #64h
AL300 november 28 , 2001 48 62h: input line rate high (r only) [linerate] li nerateh <3:0> bits <11:8> of input line rate, which is in terms of how many reference lock cycle per horizontal line. 63h: input vertical line total low (r only) [invtotal] invtotall <7:0> bits <7:0> of total vertical line count of input video refresh r ate = (reference clock frequency) / (linerate x invtotal) reference clock is the clock from xin pin. linerate is the input line rate defined in registers #61h and #62h invtotal is the input vertical total line defined in registers #63h and #64h 64h: in put vertical line total high (r only) [invtotal] invtotalh <3:0> bits <11:8> of total vertical line count of input video 65h: interrupt status (r only) [ireqstatus] newhsyncrate<0> 1, if hsync line rate of input video changes. reset by clearing the rel ated bit of register #40h, then enable it if desired. newvysnc <1> 1, if vsync of input video happens. reset by clearing the related bit of register #40h, then enable it if desired. newfield <2> 1, if odd field of input video comes. reset by clearing the related bit of register #40h, then enable it if desired. 66h: input horizontal pixel total low (r only) [inhtotal] inhtotall <7:0> bits<7:0> of total horizontal pixel count of input video 67h: input horizontal pixel total high (r only) [inhtotal] inht otalh <2:0> bits<10:8> of total horizontal pixel count of input video the two registers can be used to reconfirm if the input pixel - total number is reasonable or as expected. for instance, an odd number may indicate that the pll of the preceding adc may not have worked as how it is programmed. automatic positioning: 70h: horizontal line number for hdest & hdeend detection (r/w) [hlinenumber] hlinenumber <7:0> horizontal line number for horizontal active start and end detection; refer to register #71h for additional reference. (unit: 8 lines) 71h: data threshold (r/w) [datathreshold] datathreshold <6:0> luma (brightness) threshold value. datathreshold is used to determine whether an input pixel exists for both horizontal and vertical directions. any pixel luma value less than this value is regarded as blank. lineposdetect <7> 0 whole frame active data detection. 1 single line/column active data detection.
AL300 november 28 , 2001 49 when lineposdetect is 1, the horizontal line used to detect horizontal active start and end is defined in register 70h, and the vertical column used to detect vertical active start and end is defined in register 79h. values of register #72h~#75h reflect the detected input active pixels start/end positions or the ghref signal star/end positions, depending on the status of register #82h<7:6>. 72h: horizontal active start low (r only) [hdestart] hdestartl <7:0> bits <7:0> of detected horizontal active start pixel position. (unit: 1 pixel) 73h: horizontal active start high (r only) [hdestart] hde starth <2:0> bits <10:8> of detected horizontal active start pixel position. 74h: horizontal active end low (r only) [hdeend] hdeendl <7:0> bits <7:0> of detected horizontal active end pixel position (unit: 1 pixel) 75h: horizontal active end high (r only) [hdeend] hdeendh <2:0> bits <10:8> of detected horizontal active end pixel position. 79h: vertical column for vdestart & vdeend detection (r/w) [vcolumn] vcolumn <7:0> vertical column number for vertical active start and end detection; refer to register #71h for additional reference. (unit: 8 pixels) 7ah: vertical active start low (r only) [vdestart] vdestartl <7:0> bits <7:0> of detected vertical active start line (unit: 1 line) 7bh: vertical active start high (r only) [vdestart] vdesta rth <2:0> bits <10:8> of detected vertical active start line 7ch: vertical active end low (r only) [vdeend] vdeendl <7:0> bits <7:0> of detected vertical active end line (unit: 1 line) 7dh: vertical active end high (r only) [vdeend] vdeendh <2:0> bit s <10:8> of detected vertical active end line osd control: 80h: osd modes (r/w) [osdmode] rommode <0> enable rom mode 0 internal ram mode 1 external rom mode this bit should be 0 when osd1 and osd2 are both disabled. bypasshpos <5> 0 the output horizontal start/end position is defined by register #33h & #34h, which resolution is 8 - pixel. 1 the output horizontal start/end position is defined by registers #20h~22h
AL300 november 28 , 2001 50 softgraref <6> 0 graphic horizontal capture start is defined by the hardwa re ghref pin 1 graphic horizontal capture start is defined by register #20h and #21h. the counterpart for controlling graphic reference is defined by softtvref (register #06h<6>) 81h: logic operation (r/w) [foreop] color0op <1:0> logic operation betw een color 0 and video 00 nop show only osd 01 or video or color 0 10 and video and color 0 11 xor video xor color 0 color1op <3:2> logic operation between color 1 and video 00 nop show only osd 01 or video or color 1 10 and video and color 1 11 xor video xor color 1 color2op <5:4> logic operation between color 2 and video 00 nop show only osd 01 or video or color 2 10 and video and color 2 11 xor video xor color 2 color3op <7:6> logic operation between color 3 and vid eo 00 nop show only osd 01 or video or color 3 10 and video and color 3 11 xor video xor color 3 color 0, 1, 2 and 3 are defined in registers b0h ~ bbh. 82h: fading alpha value (r/w) [fadealpha] fadealpha <5:0> the alpha factor for fadin g effect ranging from 00h to 20h, i.e., there is 33 - level of fade - in/fade - out effect. output = input * alpha + osd * (1 ? (alpha/32)) 000000 - minimum alpha value. show only osd. 100000 - maximum alpha value. show only video ghrefpol <7:6> 00 auto positioning registers #72h~#75h controlled by hardware internal detection. 01 reserved 10 auto positioning registers #72h~#75h controlled by ghref pin, if ghref is active high. 11 auto positioning registers #72h~#75h controlled by ghref pin, if ghref is active low. on screen display 1 registers: 84h: osd1 control (r/w) [osdcontrol1] pixdepth1 <0> number of bits per pixel of on screen display (osd) 1
AL300 november 28 , 2001 51 0 one bit per pixel 1 two bits per pixel blinken1 <1> osd1 blinking enable, eff ective only when rommode = ?1?. 0 disable blinking 1 enable blinking hzoom1 <3:2> osd1 horizontal zoom factor 00 osd pixel h size equals to 1x of video pixel 01 osd pixel h size equals to 2x of video pixel 10 osd pixel h size equals to 4x o f video pixel 11 osd pixel h size equals to 8x of video pixel vzoom1 <5:4> osd1 vertical zoom factor 00 osd line v size equals to 1x of video line 01 osd line v size equals to 2x of video line 10 osd line v size equals to 4x of video line 1 1 osd line v size equals to 8x of video line font2byte1 <6> two - byte font charter code mode, effective only when rommode = ?1? 0 one - byte character code mode 1 two - byte character code mode please refer to osd data addressing in rom mode diagra m (AL300 - 11) osden1 <7> on screen display (osd) 1 enable 0 disable osd1 ; 80h<0> should be 0 when osd1 and osd2 are both disabled. 1 enable osd1 85h: osd1 rom start address (r/w) [romstartaddr1] romstaddr1h <7:0> bits<11:4> of osd1 rom start addr ess (unit: 16 bytes) bits<3:0> of osd1 rom start address is defined in register #86h<3:0> osd1 rom start address = romstaddr1h * 256 + romstaddr1l * 16 86h: osd1 font address unit (r/w) [fontaddrunit1] fontaddrunit1 <7:4> osd1 font address unit 0000 font address is multiple of 2 5 bytes 0001 font address is multiple of 2 6 bytes 0010 font address is multiple of 2 7 bytes 0011 font address is multiple of 2 8 bytes 0100 font address is multiple of 2 9 bytes 0101 font address is multiple of 2 10 bytes 0110 font address is multiple of 2 11 bytes 0111 font address is multiple of 2 12 bytes 1000 font address is multiple of 2 13 bytes 1001 font address is multiple of 2 14 bytes 1010 font address is multiple of 2 15 bytes 1011 font address is multiple of 2 16 bytes romstaddr1l <3:0> bits<3:0> osd1 rom start address (unit: 16 bytes) font address = (character code) * (font address unit) + (osd1 rom start address) ?character code? is the data retrieved from internal osd ram.
AL300 november 28 , 2001 52 ?font addre ss unit? is defined in register #86h. ?osd1 rom start address? is defined in registers #85h and #86h . 90h: osd1 horizontal start (r/w) [osdhstart1] osdhstart1 <7:0> on screen display horizontal start position (unit: 8 video pixels) relative to displa y hsync start please also refer to osd screen timing diagram (AL300 - 15) for additional reference. 91h: osd1 vertical start (r/w) [osdvstart1] osdvstart1 <7:0> on screen display vertical start position (unit: 8 video lines) relative to display vsync start please also refer to osd screen timing diagram (AL300 - 15) for additional reference. 92h: osd1 ram start address (r/w) [ramaddrst1] ramaddrst1 <7:0> osd1 ram start address (unit: 4 or 8 bytes) osd1 ram start address = 1. register 92h<7:0> * 4, if register 84h<6> = 0 2. register 92h<7:0> * 8, if register 84h<6> = 1 AL300 has built in 1k byte ram in ram mode (register 80h<0> = 0): ram start address defines the start address of stored internal osd ram bitmap. in rom mode (register 80h<0> = 1): ram start address defines the start address of osd rom font character codes retrieved from internal osd ram. font address = (character code) * (font address unit) + (osd1 rom start address) ?character code? is the data retrieved from internal os d ram. ?font address unit? is defined in register #86h. ?osd1 rom start address? is defined in register #85h. 93h: osd1 ram horizontal stride low (r/w) [ramstride1] ramstride1l <7:0> bits<7:0> of osd1 ram line stride (unit: 1 bytes) in ram mode (regis ter 80h<0> = 0): ram horizontal stride defines the number of bytes occupied in internal osd ram for each osd bitmap line. total bitmap bytes stored in osd ram: ?ram horizontal stride? x ?bitmap vertical size? (bytes) where ?ram horizontal stride ? is defined by register #8bh and #93h. ?bitmap vertical size? is defined by register #98h and #99h. in rom mode (register 80h<0> = 1): ram horizontal stride defines the total bytes occupied in internal osd ram for each osd text row. total charact er code bytes stored in osd ram: ?ram horizontal stride? x ?icon vertical total? (bytes) total character code bytes retrieved in osd ram: ?icon horizontal total? x ?icon vertical total? x ?character code size? (bytes)
AL300 november 28 , 2001 53 where ?ram horizontal stri de? is defined in register #8bh and #93h. ?icon horizontal total? is defined in register #9ch. ?icon vertical total? is defined in register #9dh. ?character code size? is defined in register #84h<6>. 8bh: osd1 ram horizontal stride high (r/w) [rams tride1] ramstride1h <1:0> bits <9:8> of osd1 ram line stride (unit: 1 bytes) the lower byte is defined by register #93h. 94h: osd1 bitmap horizontal size low (r/w) [bmaphsize1] bmaphsize1 = actual bitmap horizontal size ? 1 bmaphsize1l <7:0> bits<7:0> of osd1 horizontal bitmap size (unit: 1 osd pixel) value of (?bitmap horizontal total? ? ?bitmap horizontal size?) defines the extra gap between each character shown on osd screen. ?bitmap horizontal size? is defined by register #94h and #95h. ?bitmap horizontal total? is defined by register #96h and #97h. please refer to osd screen timing diagram (AL300 - 15) for additional reference. 95h: osd1 bitmap horizontal size high (r/w) [bmaphsize1] bmaphsize1 = actual bitmap horizontal size ? 1 bmaphsize1h < 1:0> bits<9:8> of osd1 bitmap horizontal size the lower byte is defined by register #94h. 96h: osd1 bitmap horizontal total pixels low (r/w) [bmaphtotal1] bmaphtotal1 = actual bitmap horizontal total ? 1 bmaphtotal1l <7:0> bits<7:0> of osd1 bitmap hori zontal total (unit: 1 osd pixel) value of (?bitmap horizontal total? ? ?bitmap horizontal size?) defines the extra gap between each character shown on osd screen. ?bitmap horizontal size? is defined by register 94h and 95h. ?bitmap horizontal total? is defined by register 96h and 97h. please refer to osd screen timing diagram (AL300 - 15) for additional reference. 97h: osd1 bitmap horizontal total pixels high (r/w) [bmaphtotal1] bmaphtotal1 = actual bitmap horizontal total ? 1 bmaphtotal1h <1:0> bits <9:8> of osd1 bitmap horizontal total the lower byte is defined by register #96h. 98h: osd1 bitmap vertical size low (r/w) [bmapvsize1] bmapvsize1 = actual bitmap vertical size ? 1 bmapvsize1l <7:0> bits<7:0> of osd1 bitmap vertical size (unit: 1 osd line) value of (?bitmap vertical total? ? ?bitmap vertical size?) defines the extra line(s) between each text row shown on osd screen. ?bitmap vertical size? is defined by register #98h and #99h. ?bitmap vertical total? is defined by register #9ah and # 9bh. please refer to osd screen timing diagram (AL300 - 15) for additional reference.
AL300 november 28 , 2001 54 99h: osd1 bitmap vertical size high (r/w) [bmapvsize1] bmapvsize1 = actual bitmap vertical size ? 1 bmapvsize1h <1:0> bits<9:8> of osd1 bitmap vertical size the lower byte is defined by register #98h. 9ah: osd1 bitmap vertical total lines low (r/w) [bmapvtotal1] bmapvtotal1 = actual bitmap vertical total ? 1 bmapvtotal1l <7:0> bits<7:0> of osd1 bitmap vertical total (unit: 1 osd line) value of (?bitmap vertical tot al? ? ?bitmap vertical size?) defines the extra line(s) between each text row shown on osd screen. ?bitmap vertical size? is defined by register #98h and #99h. ?bitmap vertical total? is defined by register #9ah and #9bh. please refer to osd screen timi ng diagram (AL300 - 15) for additional reference. 9bh: osd1 bitmap vertical total lines high (r/w) [bmapvtotal1] bmapvtotal1 = actual bitmap vertical total ? 1 bmapvtotal1h <1:0> bits<9:8> of osd1 bitmap vertical total the lower byte is defined by regist er #9ah. 9ch: osd1 icon horizontal total (r/w) [iconhtotal1] iconhtotal1 = actual icon horizontal total ? 1 iconhtotal1 <7:0> osd1 horizontal icon total (unit: 1 icon) icon horizontal total defines how many character codes should be retrieved from internal osd ram and shown on osd screen per osd line. total character code bytes stored in osd ram: ?ram horizontal stride? x ?icon vertical total? (bytes) total character code bytes retrieved in osd ram: ?icon horizontal total? x ?icon vertical tot al? x ?character code size? (bytes) where ?ram horizontal stride? is defined by register #8bh and #93h. ?icon horizontal total? is defined by register #9ch. ?icon vertical total? is defined by register #9dh. ?character code size? is defined by regist er #84h<6>. please refer to osd screen timing diagram (AL300 - 15) for additional reference. 9dh: osd1 icon vertical total (r/w) [iconvtotal1] iconvtotal1 = actual vertical icon total ? 1 iconvtotal1 <7:0> osd1 vertical icon total (unit: 1 icon) icon ve rtical total defines how many text rows shown on osd screen. total character code bytes stored in osd ram: ?ram horizontal stride? x ?icon vertical total? (bytes) total character code bytes retrieved in osd ram: ?icon horizontal total? x ?icon vertic al total? x ?character code size? (bytes) where ?ram horizontal stride? is defined by register #8bh and #93h. ?icon horizontal total? is defined by register #9ch.
AL300 november 28 , 2001 55 ?icon vertical total? is defined by register #9dh. ?character code size? is defined by register #84h<6>. please refer to osd screen timing diagram (AL300 - 15) for additional reference. aeh: osd1 font line size (r/w) [fontlinesize1] fontlinesize1 <7:0> memory size of a line of font (unit: 1 byte) registers #94h and #95h define the size b y bits, but #aeh defines it by bytes. on screen display 2 registers: 88h: osd2 control (r/w) [osdcontrol2] pixdepth2 <0> number of bits per pixel of on screen display (osd) 2 0 one bit per pixel 1 two bits per pixel blinken2 <1> osd2 blin king enable, effective only when rommode = ?1?. 0 disable blinking 1 enable blinking hzoom2 <3:2> osd2 horizontal zoom factor 00 osd pixel h size equals to 1x of video pixel 01 osd pixel h size equals to 2x of video pixel 10 osd pixel h siz e equals to 4x of video pixel 11 osd pixel h size equals to 8x of video pixel vzoom2 <5:4> osd2 vertical zoom factor 00 osd line v size equals to 1x of video line 01 osd line v size equals to 2x of video line 10 osd line v size equals to 4x of video line 11 osd line v size equals to 8x of video line font2byte2 <6> two - byte font charter code mode, effective only when rommode = ?1? 0 one - byte character code mode 1 two - byte character code mode please refer osd data addressing in ro m mode diagram (AL300 - 11) osden2 <7> on screen display (osd) 2 enable 0 disable osd2 ; 80h<0> should be 0 when osd1 and osd2 are both disabled. 1 enable osd2 89h: osd2 rom start address (r/w) [romstartaddr2] romstaddr2h <7:0> bits<11:4> of osd2 r om start address (unit: 16 bytes) bits<3:0> of osd2 rom start address is defined in register #8ah<3:0> osd1 rom start address = romstaddr1h * 256 + romstaddr1l * 16 8ah: osd2 font address unit (r/w) [fontaaddrunit2] fontaddrunit2 <7:4> osd2 font a ddress unit 0000 font address is multiple of 2 5 bytes 0001 font address is multiple of 2 6 bytes
AL300 november 28 , 2001 56 0010 font address is multiple of 2 7 bytes 0011 font address is multiple of 2 8 bytes 0100 font address is multiple of 2 9 bytes 0101 font addres s is multiple of 2 10 bytes 0110 font address is multiple of 2 11 bytes 0111 font address is multiple of 2 12 bytes 1000 font address is multiple of 2 13 bytes 1001 font address is multiple of 2 14 bytes 1010 font address is multiple of 2 15 bytes 1011 font address is multiple of 2 16 bytes romstaddr2l <3:0> bits<3:0> osd2 rom start address (unit: 16 bytes) font address = (character code) * (font address unit) + (osd2 rom start address) ?character code? is the data retrieved from internal osd ram. ?font address unit? is defined by register #8ah. ?osd2 rom start address? is defined by register #89h and #8ah . a0h: osd2 horizontal start (r/w) [osdhstart2] osdhstart2 <7:0> on screen display horizontal start position (unit: 8 video pixels) re lative to display hsync start please refer to osd screen timing diagram (AL300 - 15) for additional reference. a1h: osd2 vertical start (r/w) [osdvstart2] osdvstart2 <7:0> on screen display vertical start position (unit: 8 video lines) relative to disp lay vsync start please refer to osd screen timing diagram (AL300 - 15) for additional reference. a2h: osd2 ram start address (r/w) [ramaddrst2] ramaddrst2 <7:0> osd2 ram start address (unit: 4 or 8 bytes) osd2 ram start address = 1. register a2h<7:0> * 4, if register 88h<6> = 0 2. register a2h<7:0> * 8, if register 88h<6> = 1 AL300 has built in 1k byte ram in ram mode (register 80h<0> = 0): ram start address defines the start address of stored internal osd ram bitmap. in rom mode (register 80h< 0> = 1): ram start address defines the start address of osd rom font character codes retrieved from internal osd ram. font address = (character code) * (font address unit) + (osd2 rom start address) where ?character code? is the data retrieved from internal osd ram. ?font address unit? is defined by register #8ah. ?osd2 rom start address? is defined by register #89h. a3h: osd2 ram horizontal stride low (r/w) [ramstride2] ramstride2l <7:0> bits<7:0> of osd2 ram line stride (unit: 1 bytes) in r am mode (register 80h<0> = 0):
AL300 november 28 , 2001 57 ram horizontal stride defines the amount of bytes occupied in internal osd ram for each osd bitmap line. total bitmap bytes stored in osd ram: ?ram horizontal stride? x ?bitmap vertical size? (bytes) where ?ram horizontal stride? is defined by registers #8ch and #a3h. ?bitmap vertical size? is defined by registers #a8h and #a9h. in rom mode (register 80h<0> = 1): ram horizontal stride defines the total bytes occupied in internal osd ram for each osd text r ow. total character code bytes stored in osd ram: ?ram horizontal stride? x ?icon vertical total? (bytes) total character code bytes retrieved in osd ram: ?icon horizontal total? x ?icon vertical total? x ?character code size? (bytes) where ?ram horizontal stride? is defined by register #8bh and #93h. ?icon horizontal total? is defined by register #9ch. ?icon vertical total? is defined by register #9dh. ?character code size? is defined by register #84h<6>. please refer to osd scree n timing diagram (AL300 - 15) for additional reference. 8ch: osd2 ram horizontal stride high (r/w) [ramstride2] ramstride2h <1:0> bits<9:8> of osd2 ram line stride (unit: 1 bytes) refer to register #a3h for additional reference. a4h: osd2 bitmap horizont al size low (r/w) [bmaphsize2] bmaphsize2 = actual bitmap horizontal size ? 1 bmaphsize2l <7:0> bits<7:0> of osd2 horizontal bitmap size (unit: 1 osd pixel) value of (?bitmap horizontal total? ? ?bitmap horizontal size?) defines the extra gap between ea ch character shown on osd screen. ?bitmap horizontal size? is defined by registers #a4h and #a5h. ?bitmap horizontal total? is defined by registers #a6h and #a7h. please refer to osd screen timing diagram (AL300 - 15) for additional reference. a5h: osd2 bitmap horizontal size high (r/w) [bmaphsize2] bmaphsize2 = actual bitmap horizontal size ? 1 bmaphsize2h <1:0> bits<9:8> of osd2 bitmap horizontal size the lower byte is defined by register #a4h. a6h: osd2 bitmap horizontal total pixels low (r/w) [bma phtotal2] bmaphtotal2 = actual bitmap horizontal total ? 1 bmaphtotal2l <7:0> bits<7:0> of osd2 bitmap horizontal total (unit: 1 osd pixel) value of (?bitmap horizontal total? ? ?bitmap horizontal size?) defines the extra gap between each character show n on osd screen. ?bitmap horizontal size? is defined by registers #a4h and #a5h. ?bitmap horizontal total? is defined by registers #a6h and #a7h.
AL300 november 28 , 2001 58 please refer to osd screen timing diagram (AL300 - 15) for additional reference. a7h: osd2 bitmap horizont al total pixels high (r/w) [bmaphtotal2] bmaphtotal2 = actual bitmap horizontal total ? 1 bmaphtotal2h <1:0> bits<9:8> of osd2 bitmap horizontal total the lower byte is defined by register #a6h. a8h: osd2 bitmap vertical size low (r/w) [bmapvsize2] bm apvsize2 = actual bitmap vertical size ? 1 bmapvsize2l <7:0> bits<7:0> of osd1 bitmap vertical size (unit: 1 osd line) value of (?bitmap vertical total? ? ?bitmap vertical size?) defines the extra line(s) between each text row shown on osd screen. ?bitm ap vertical size? is defined by registers #a8h and #a9h. ?bitmap vertical total? is defined by registers #aah and #abh. please refer to osd screen timing diagram (AL300 - 15) for additional reference. a9h: osd2 bitmap vertical size high (r/w) [bmapvsize2] bmapvsize2 = actual bitmap vertical size ? 1 bmapvsize2h <1:0> bits<9:8> of osd2 bitmap vertical size the lower byte is defined by register #a8h. aah: osd2 bitmap vertical total lines low (r/w) [bmapvtotal2] bmapvtotal2 = actual bitmap vertical total ? 1 bmapvtotal2l <7:0> bits<7:0> of osd2 bitmap vertical total (unit: 1 osd line) value of (?bitmap vertical total? ? ?bitmap vertical size?) defines the extra line(s) between each text row shown on osd screen. ?bitmap vertical size? is defined by regi sters #a8h and #a9h. ?bitmap vertical total? is defined by registers #aah and #abh. please refer to osd screen timing diagram (AL300 - 15) for additional reference. abh: osd2 bitmap vertical total lines high (r/w) [bmapvtotal2] bmapvtotal2 = actual bitma p vertical total ? 1 bmapvtotal2h <1:0> bits<9:8> of osd2 bitmap vertical total the lower byte is defined by register #aah. ach: osd2 icon horizontal total (r/w) [iconhtotal2] iconhtotal2 = actual icon horizontal total ? 1 iconhtotal2 <7:0> osd1 h orizontal icon total (unit: 1 icon) icon horizontal total defines how many character codes should be retrieved from internal osd ram and shown on osd screen per osd line. total character code bytes stored in osd ram: ?ram horizontal stride? x ?icon ve rtical total? (bytes) total character code bytes retrieved in osd ram: ?icon horizontal total? x ?icon vertical total? x ?character code size? (bytes) where ?ram horizontal stride? is defined by registers #8ch and #a3h. ?icon horizontal total? is defined by register #ach.
AL300 november 28 , 2001 59 ?icon vertical total? is defined by register #adh. ?character code size? is defined by register #88h<6>. please refer to osd screen timing diagram (AL300 - 15) for additional reference. adh: osd2 icon vertical total (r/w) [ic onvtotal2] iconvtotal2 = actual vertical icon total ? 1 iconvtotal2 <7:0> osd2 vertical icon total (unit: 1 icon) icon vertical total defines how many text rows shown on osd screen. total character code bytes stored in osd ram: ?ram horizontal strid e? x ?icon vertical total? (bytes) total character code bytes retrieved in osd ram: ?icon horizontal total? x ?icon vertical total? x ?character code size? (bytes) where ?ram horizontal stride? is defined by registers #8ch and #a3h. ?icon horizon tal total? is defined by register #ach. ?icon vertical total? is defined by register #adh. ?character code size? is defined by register #88h<6>. please refer to osd screen timing diagram (AL300 - 15) for additional reference. afh: osd2 font line size (r/w) [fontlinesize2] fontlinesize2 <7:0> memory size of a line of font (unit: 1 byte) please refer to osd screen timing diagram (AL300 - 15) for additional reference. on screen display color registers: color 0 is the color of pixel with value: ?0? whe n in 1 - bit/2 - color mode or ?00? when in 2 - bit/4 - color mode. color 1 is the color of pixel with value: ?1? when in 1 - bit/ 2 - color mode or ?01? when in 2 - bit/4 - color mode. color 2 is the color of pixel with value ?10? when in 2 - bit, 4 - color mode. color 3 is the color of pixel with value ?11? when in 2 - bit, 4 - color mode. b0h: color 0 red (r/w) [color0red] color0red <7:0> color 0 red component b1h: color 0 green (r/w) [color0green] color0green <7:0> color 0 green component b2h: color 0 blue (r/w) [color0 blue] color0blue <7:0> color 0 blue component b3h: color 1 red (r/w) [color1red] color1red <7:0> color 1 red component b4h: color 1 green (r/w) [color1green]
AL300 november 28 , 2001 60 color1green <7:0> color 1 green component b5h: color 1 blue (r/w) [color1blue] color1blue < 7:0> color 1 blue component b6h: color 2 red (r/w) [color2red] color2red <7:0> color 2 red component b7h: color 2 green (r/w) [color2green] color2green <7:0> color 2 green component b8h: color 2 blue (r/w) [color2blue] color2blue <7:0> color 2 blue c omponent b9h: color 3 red (r/w) [color3red] color3red <7:0> color 3 red component bah: color 3 green (r/w) [color3green] color3green <7:0> color 3 green component bbh: color 3 blue (r/w) [color3blue] color3blue <7:0> color 3 blue component
AL300 november 28 , 2001 61 8.2 prog ramming flowchart interrup? (check reg.#65h or mode change) 1. set reference timing (reg#03h<7>, 41h & 42h) 2. set up osd for warning define proper values for input/output timing based on input signals: - read vtotal(reg.#63h,64h) and linerate(reg.#61h,62h) -read predefined input/output timing values in eeprom or do auto-positioning detection(reg.#70h~7dh) - set input timing registers (reg.#20h~22h, 24h~29h) - set output timing registers (reg.#30h~35h, 37h~3ah) - set zooming/phase/delay registers (reg.#14h~1ah, 3bh and 3ch) - program adc or decoder if necessary - program output pll (reg.#10h~13h) adjust clock phase of the adc (al875) to minimize jitters if necessary wait until output display is stable (delay for 100 ms) enable lcd panel output set reg.#40h = 01h to enable interrupt 1. wait until AL300 stablizes by checking if reg.#00h=46h 2. set reg.#40h=07h to force interrupt 3. initialize video decoder if necessary disable lcd panel output set reg#40h = 00h to clear interrupt video/graphic input exists? (check reg.#61h~64h) yes yes no no AL300-25 programming flowchart_ver b input stable? (check reg.#61h~64h) yes no
AL300 november 28 , 2001 62 9.0 mechanical drawing AL300: 28mm x 28mm 160 - pin 0.65 - pitch pqfp package
AL300 november 28 , 2001 63 10.0 power consumption the AL300 works at single 3.3v power. the following table shows the current consumption of the AL300 (with output buffers to the pan el) at different operating frequencies and supply voltages. output frequency current consumption AL300@3.3v 110mhz 135 ma (typ.) AL300@3.3v 70mhz 95 ma (typ.) AL300@3.3v 50mhz 75 ma (typ.) AL300@3.3v 30mhz 55 ma (typ.) power down 5 ma (typ.) the current consumption may be somewhat higher when the output of the AL300 drives a panel directly. for more information about the AL300 or other averlogic products, please contact your local authorized representatives, visit our website, or contact us direc tly.
contact information averlogic technologies, inc. 6840 via del oro suite 160 san jose, ca 95119 usa tel : 1 408 361 - 0400 fax : 1 408 361 - 0404 e - mail : sales@averlogic.com url : www.averlogic.com